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?005 fairchild semiconductor corporation 1 www.fairchildsemi.com f ebruary 2005 ml6554 rev. 1.1.5 ml6554 3a bus termination regulator ml6554 3a bus termination regulator features can source and sink up to 3a, no heat sink required integrated power mosfets generates termination voltages for ddr sdram, sstl-2 sdram, sgram, or equivalent memories generates termination voltages for active termination schemes for ddr sdram, gtl+, rambus, vme, lv -ttl, hstl, pecl and other high speed logic v ref input available for external voltage divider separate voltages for v ccq and pv dd buffered v ref output v out of ?% or less at 3a minimum external components shutdown for standby or suspend mode operation 0?to +70? and -40?to +85? temperature ranges available thermal shutdown 130? description the ml6554 switching regulator is designed to convert voltage supplies ranging from 2.3v to 4v into a desired output voltage or termination voltage for various applications. the ml6554 can be implemented to produce regulated output voltages in two dif- fe rent modes. in the default mode, when the v ref pin is open, the ml6554 output voltage is 50% of the voltage applied to v ccq . the ml6554 can also be used to produce various user- de?ed voltages by forcing a voltage on the vref in pin. in this case, the output voltage follows the input vref in volt age. the sw itching regulator is capable of sourcing or sinking up to 3a of current while regulating an output v tt vo ltage to within 3% or less. the ml6554, used in conjunction with series termination resisi- tors, provides an excellent voltage source for active termination schemes of high speed transmission lines as those seen in high speed memory buses and distributed backplane designs. the vo ltage output of the regulator can be used as a termination vo ltage for other bus interface standards such as ddr sdram, sstl, cmos, rambus , gtl+, vme, lv-cmos, lv-ttl, hstl and pecl. block diagram v l2 agnd 13 vref in vref out 11 6 v dd 1 shdn 12 pv dd2 pv dd1 7 v l1 3 + + av cc v ccq 15 oscillator/ ramp generator s r q q (v out ) (v out ) p gnd1 d gnd v fb p gnd2 2 4 5 8 v dd 9 14 10 v ref buffer error amp ramp comparator + 16 200k ? 200k ?
2 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator pin con?uration pin description note: the psop-16l package features an integrated heat slug and is connected to the back side of the ml6554 die which is gnd. this slug can be soldered to a gnd copper plane (agnd, pgnd1 and pgnd2) for better thermal conductivity. see ?echanical dimensions diagram for land pattern recommendation. pin name function 1v dd digital supply voltage 2pv dd1 vo ltage supply for internal power transistors 3v l1 output voltage/ inductor connection 4p gnd1 ground for output power transistors 5p gnd2 ground for output power transistors 6v l2 output voltage/inductor connection 7pv dd2 vo ltage supply for internal power transistors 8d gnd digital ground 9v dd digital supply voltage 10 v fb input for external compensation feedback 11 vref in input for external reference voltage 12 shdn shutdown active low. cmos input level 13 agnd ground for internal reference voltage divider 14 vref out reference voltage output 15 v ccq vo ltage reference for internal voltage divider 16 av cc analog voltage supply ml6554 16-pin psop (u16) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view v dd pv dd1 v l1 p gnd1 p gnd2 v l2 pv dd2 d gnd av cc v ccq vref out agnd shdn vref in v fb v dd
3 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator absolute maximum ratings absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device operation is not implied. operating conditions electrical characteristics unless otherwise speci?d, av cc = v dd = pv dd = 3.3v ?0%, ta = operating temperature range (note 1) notes 1. limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. 2. infinite heat sink p arameter min. max. units pv dd 4.5 v vo ltage on any other pin gnd ?0.3 v in + 0.3 v av erage switch current (i avg )3.0 a j unction temperature 150 ? storage temperature range -65 150 ? lead temperature (soldering, 10 sec) 260 ? thermal resistance ( jc )(note 2) 2 ?/w output current, source or sink 3.0 a p arameter min. max. units t emperature range, cu suf? 0 70 c t emperature range, iu suf? -40 +85 ? pv dd operating range 2.0 4.0 v v ccq operating range 1.4 4.0 v symbol parameter conditions min. typ. max. units switching regulator v tt output voltage, sstl_2 (see figure 1) i out = 0, v ref = open v ccq = 2.3v 1.12 1.15 1.18 v v ccq = 2.5v 1.22 1.25 1.28 v v ccq = 2.7v 1.32 1.35 1.38 v i out = ?a, v ref = open v ccq = 2.3v 1.09 1.15 1.21 v v ccq = 2.5v 1.19 1.25 1.31 v v ccq = 2.7v 1.28 1.35 1.42 v vref out internal resistor divider i out = 0 v ccq = 2.3v 1.139 1.15 1.162 v v ccq = 2.5v 1.238 1.25 1.263 v v ccq = 2.7v 1.337 1.35 1.364 v z in v ref reference pin input impedance v ccq = 0 100 k ? switching frequency 650 khz ? v offset offset voltage v tt ?vref out av cc = 2.5v no load v ccq = 2.5 ?0 20 mv supply i q quiescent current i out = 0, no load v ccq = 2.5v i vccq 610a i a vcc 0.5 1.0 ma i a vcc sd 0.2 0.5 ma i vdd 0.25 1.0 ma i vdd sd 0.2 1.0 ma i pvdd 100 250 ? buffer i ref output load current 3 ma
4 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator functional description this switching regulator is capable of sinking and sourcing 3a of current without an external heatsink. the ml6554 uses a power surface mount package (psop) that includes an integrated heat slug which is inherently connected to gnd. the heat can be piped through the bottom of the device and onto the pcb (fig- ure 1). the ml6554 integrates two power mosfets that can be used to source and sink 3a of current while maintaining a tight volt- age regulation. using the external feedback, the output can be regulated well within 3% or less, depending on the external components chosen. separate voltage supply inputs have been added to accommodate applications with various power sup- plies for the databus and power buses, see figure 2. outputs the output voltage pins (v l1 , v l2 ) are tied to the databus, address, or clock lines via an external inductor. see the applica- tions section for recommendations. output voltage is deter- mined by the v ccq or vref in inputs. inputs the input voltage pins (v ccq or vref in ) determine the output vo ltages (v l1 or v l2 ) . in the default mode, where the vref in pin is ?ating, the output voltage is 50% of the v ccq input. v ccq can be the reference voltage for the databus. output voltage can also be selected by forcing a voltage at the vref in pin. in this case, the output voltage follows the voltage at the vref in input. simple voltage dividers can be used this case to produce a wide variety of output voltages between 0.7v and v dd ?.7v. vref input and output the vref in input can be used to force a voltage at the outputs (inputs section, above). the vref out pin is an output pin that is driven by a small output buffer to provide the v ref signal to other devices in the system. the output buffer is capable of driv- ing several output loads. the output buffer can handle 3ma. other supply voltages several inputs are provided for the supply voltages: pv dd1 , pv dd2 , av cc , and v dd . the pv dd1 and pv dd2 provide the power supply to the power mosfets. v dd provides the voltage supply to the digital sec- tions, while av cc supplies the voltage for the analog sections. again, see the applications section for recommendations. feedback input the v fb pin is an input that can be used for closed loop com- pensation. this input is derived from the voltage output. see application section for recommendation. figure 1. cutaway view of psop package heat slug connect this slug to a gnd plane for better thermal conductivity.
5 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator applications using the ml6554 for sstl bus termination the circuit schematic in figure 2 shows a recommended approach for constructing a bus terminating solution for an sstl-2 bus. this circuit can be used in pc memory and graph- ics memory applications as shown in figures 4 and 5. note that the ml6554 can provide the voltage reference (v ref ) and termi- nating voltages (v tt ). using the layout as shown in figures 6, 7, and 8, and measuring the v tt performance using the test setup as described in figure 9, the ml6554 delivered a v tt ?20mv fo r 1a to 3a loads (see figure 10). table 1 provides a recom- mended parts list for the circuit in figure 2. po wer handling capability of the psop package using the board layout shown in figures 6, 7, and 8; soldering the ml6554 to the board at zero lfpm the temperature around the package measured 55? for 3a loads. note that a 1 ounce copper plane was used in the board construction. air?w is not likely to be needed in the operation of this device (assuming a board layout similar to that described above). the power handling performance of the psop package is shown by a study of the package manufacturer for various air?w vs. ja conditions in figure 11. bus termination solutions for others buses ta bl e 3 provides a summary of various bus termination v ref & v tt requirements. the ml6554 can be used for those applica- tions. figure 2. typical application circuit 16 15 14 13 12 11 10 9 u1 ml6554 v dd pv dd1 v l1 p gnd1 p gnd2 v l2 pv dd2 d gnd av cc v ccq vref out a gnd shdn vref in v fb v dd 1 2 3 4 5 6 7 8 r3 100k ? v ccq vref out tpi v tt 2.5v to 4v shdn vref in gnd gnd to sdrams c6 c7 1nf c5 330 f 330 f c4 0.1 f r4 100k ? r5 1k ? c9 0.1 f r2 100 ? r1 100 ? c8 0.1 f c2 0.1 f c1 820 f f2v os-con l1 3.3 h c3 0.1 f
6 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator figure 3. alternate application circuit an alternate application circuit for the ml6554 is shown in fig- ure 3. the number of external components is reduced com- pared to the circuit in figure 2. this is achieved by replacing f our, 0.1? bypass capacitors with one, low esr, 10? ceramic capacitor placed right next to u1. two 100 ? r esistors are also eliminated. high value, surface-mount mlc capacitors were not av ailable when the original application circuit (figure 2) was developed. both application circuits offer the same electrical performance but that shown in figure 2 has a reduced bill-of- materials. table 2 shows the recommended parts list for the cir- cuit of figure 3. 16 15 14 13 12 11 10 9 u1 ml6554 v dd pv dd1 v l1 p gnd1 p gnd2 v l2 pv dd2 d gnd av cc v ccq vref out a gnd shdn vref in v fb v dd 1 2 3 4 5 6 7 8 r3 100k ? v ccq vref out v tt 2.5v to 4v shdn vref in gnd gnd to sdrams c6 c4 1nf c5 330 f 330 f r1 100k ? r2 1k ? c2 0.1 f c1 820 f f2v os-con l1 3.3 h c3 10 f
7 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator figure 4. complete termination solution pc main memory (pc motherboard) figure 5. complete termination solution graphics memory bus ?agp graphics cards d ata line, clock lines, address lines, control lines termination resistors ml6554 pc chip set northbridge termination resistors vtt vref 168/184/208-pin dimm connectors and sdram/sgram modules d ata line, clock lines, address lines, control lines termination resistors 3d graphic chip termination resistors so dimm and modules sgram ml6554 voltage regulator 2.5v vref vtt 5v or 3.3v ag p/pci bus
8 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator figure 6. top silk figure 7. top layer figure 8. bottom layer
9 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator figure 9. test circuit setup figure 10. vtt performance for sstl-2 bus 3.3v power supply active clamp v dd current source/sink power supply v tt gnd v ccq va v ccq supply va ml6554 eval i tt 3a sourcing 2a sourcing 1a sourcing v tt variance with v dd @i tt (v ccq 2.5v) tested with eval pcb 3a sinking i tt 2a sinking 1a sinking 0a sinking 1.29 1.28 1.27 1.26 v tt (v) v dd (v) 2.0 2.5 3.0 4.0 3.5
10 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator ta b le 1. recommend parts list for sstl-2 termination circuit in figure 2. ta b le 2. recommend parts list for figure 3. item qty description manufacturer / part number designator resistors 12 100 ? 1210 smd panasonic/erj-8enf1000v r1, r2 211k ? 1210 smd panasonic/erj-8enf1001v r5 32 100k ? 1210 smd panasonic/erj-8enf1003v r3, r4 capacitors 43 0.1? 1210 film smd panasonic/ecv3vb1e104k p anasonic/ecu-v1h104kbw c2, c8, c9 51 820? 2v solid elect. smd sanyo/2sv820m os con c1 62 330? tant 6.3v 100m ? a vx/tpse337m006r0100 c5, c6 71 1nf 1210 film smd panasonic/ecu-v1h102kbm c7 82 0.1? 0805 film panasonic/ecj-2vf1c104z c3, c4 ics 91 ml6554 bus terminator po we r sop package ml6554cu or ml6554iu u1 magnetics 10 1 3.3? 5a inductor smd coilcraft/d03316p-332hc pulse eng./ p0751.332t gowanda/smp3316-331m xfmrs inc./xf0046-s4 l1 other 11 1 scope probe socket tektronics/131-4353-00 tp1 12 1 12 pin breakaway strip sullins/ptc36saan (36 pins) i/o, standoffs item qty description manufacturer / part number designator resistors 12 100k ? 0805 smd panasonic/erj-8enf1000v r1, r3 211k ? 0805 smd panasonic/erj-8enf1000v r2 capacitors 31 0.1?, 1210 film smd panasonic/ecv3vb1e104k p anasonic/ecu-v1h104kbw c2 41 820? 2v solid elect. smd sanyo/2sv820m os con c1 52 330? tant 6.3v 100m ? a vx/tpse337m006r0100 c5, c6 61 1nf 1210 film smd panasonic/ecu-v1h102kbm c4 71 10? 6.3v ceramic tdk/c2012x5r0j106m c3 ics 81 ml6554 bus terminator po we r sop package ml6554cu or ml6554iu u1 magnetics 91 3.3? 5a inductor smd coilcraft/d03316p-332hc pulse eng./ p0751.332t gowanda/smp3316-331m xfmrs inc./xf0046-s4 l1 other 10 1 scope probe socket tektronics/131-4353-00 tp1 11 1 12 pin breakaway strip sullins/ptc36saan (36 pins) i/o, standoffs
11 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator v endor list 1. avx (207) 282-5111 2. sanyo (619) 661-6835 3. tektronix (408) 496-0800 4. coilcraft (847) 639-6400 5. pulse (800) 797-8573 6. gowanda (716) 532-2234 7. xfmrs inc. (317) 834-1066 8. panasonic (714) 373-7366 9. digikey (800) 344-4539 figure 11. graphical results summary ?1s2p test board power (w) natural convection ja test results 1.27mm pitch powersop 2 slug soldered forced convection ja test results 1.27mm pitch powersop 2 slug soldered 60 40 20 0 ja (?/w) 0.2 1.0 1.4 1.8 0.6 0.4 1.2 1.6 2.0 0.8 0.0 60 40 20 0 ja (?/w) air velocity (lfpm) 0 200 300 500 400 100 16ld psop2 2.3x3.1mm pad 1.9mm die 16ld psop2 2.3x3.1mm pad 1.9mm die @ 0.8 watts
12 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator figure 12. test board layout for ja vs. air?w ta b le 3. termination solutions summary by buss type bus description driving method vddq vtt v ref f airchild solutions industry system components gtl+ gunning tr ansceiver bus plus open drain 5v or 3.3v note 10 1.5v?0% note12 1.0v?% note 11 ml6554cu; mode: v ref input = 1.5v, v cc = 5v 300 to 500mhz processor; pc chipsets; gtlp 16xxx buffers; fairch ild, te xas instr. sstl_2 series stub te r m i nated logic for 2v symmetric drive, series resistance 2.5v?0% 0.5x (v ddq ) ?% 2.5v ml6554cu or ml6553cs; mode: v ref input = floating or forced, v cc = 3.3v sstl sdram; hitachi, fujitsu, nec, micro, mitsubishi rambus rambus signaling logic open drain none speci?d 2.5v 2.0v ml6553cs; mode: v ref input = open, v cc = v ddq ndram, rambus, intel, toshiba lv- ttl low voltage ttl logic or pecl or 3.3v vme symmetric drive 3.3?0% v ddq /2 3.3v ml6553cs; mode: v ref input = open, vcc = vddq processors or backplanes; lv- ttl sdram, edo ram drawing number eng-cb-1007 rev a applicable jedec spec jc 51-x (note 1) (proposed spec) substrate material fr-4 dimensions (lxw) (overall) 114.3 x 76.2mm dimensions (lxw) (metallization) 55 x 65mm dimensions (lxw) (inner planes) 73 x 73mm thickness 1.6 mm pitch 1.27mm stackup (# signal layers, # cu planes) 1s2p cu trace coverage (signal layer) 12% cu coverage (internal layer) 100% tr ace width (spec/measured) 235.5 25.5/288 m tr ace cu thickness (spec/measured) 70 14/67 m inner cu thickness (spec/measured) 35 3.5/31 m build # c1797 note 1: proposed spec "thermal test board with two internal solid copper planes for leaded surface mount packages".
13 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator mechanical dimensions 16-pin psop ordering information pa rt number temperature range package ml6554cu 0? to 70? 16-pin psop (u16) ml6554iu -40? to +85? 16-pin psop (u16) 9.90 0.10 3.90 0.10 8.89 1.95 1.75 1.27 1.75 max 0.70 0.20 (1.04) (r0.10) gage plane notes: unless otherwise specified a) this package conforms to jedec ms?12, variation ac, issue c, dated may 1990. b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. seating plane detail a scale: 2:1 (r0.10) 8 0 see detail a 1.45 +0.05 ?.20 0.15 0.36 x 45 0.10 c c +0.10 ?.05 0.50 0.25 7.50 2.50 7.40 3.50 8.89 land pattern recommendation 0.60 3.70 6.00 1.27 0.51 0.35 0.25 0.19 0.25 c b a m pin one indicator (0.30) 16 18 9 a b
14 www.fairchildsemi.com ml6554 rev. 1.1.5 ml6554 3a bus termination regulator disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy f airchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production intellimax? isoplanar? littlefet? microcoupler? microfet? micropak? microwire? msx? msxpro? ocx? ocxpro? optologic ? optoplanar? p acman? f ast ? f astr? fps? frfet? globaloptoisolator? gto? hisec? i 2 c? i-lo ? implieddisconnect? rev. i15 acex? activearray? bottomless? coolfet? crossvolt ? dome? ecospark? e 2 cmos? ensigna? f act? f act quiet series? pop? power247? poweredge? powersaver? powertrench ? qfet ? qs? qt optoelectronics? quiet series? rapidconfigure? rapidconnect? serdes? silent switcher ? smart start? spm? s tealth? superfet? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic ? tinyopto? trutranslation? uhc? ultrafet ? unifet? vcx? across the board. around the world.? the power franchise ? programmable active droop?

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